Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
In some memory device types, memory cells are arranged in cell strings. Each cell string comprises a group of cells that are connected back-to-back in series with one another. Cell strings are typically used, for example, in NAND Flash devices. NAND Flash devices are described, for example, by Jung et al., in “A 117 mm2 3.3 Volts Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications,” IEEE Journal of Solid State Circuits, (11:31), November, 1996, pages 1575-1583, and by Takeuchi et al., in “A Double Level VTH Select Gate Array Architecture for Multi-Level NAND Flash Memories,” Digest of Technical Papers, 1995 Symposium on VLSI Circuits, Jun. 8-10, 1995, pages 69-70, which are incorporated herein by reference.
Memory cells that are arranged in cell strings sometimes suffer from Back Pattern Dependency (BPD) distortion. BPD distortion in a given cell is typically caused by changes in the conduction properties of other cells in the string, which cause an artificial shift in the storage value read from the given cell. U.S. Pat. No. 7,310,272, whose disclosure is incorporated herein by reference, describes a memory device that accounts for back pattern effects by applying a first voltage during a verify operation for unselected word lines that have been subjected to a programming operation, and a second voltage for unselected word lines that have not been subjected to a programming operation.